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INTEGRATED CIRCUITS
DATA SHEET
SAA1101 Universal sync generator (USG)
Product specification File under Integrated Circuits, IC02 January 1990
Philips Semiconductors
Product specification
Universal sync generator (USG)
FEATURES * Programmable to seven standards * Additional outputs to simplify signal processing * Can be synchronized to an external sync. signal * Option to select the 524/624 line mode instead of the 525/625 line mode * Lock from subcarrier to line frequency GENERAL DESCRIPTION
SAA1101
The SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras, film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043 sync generator and the SAA1044 subcarrier coupling IC. QUICK REFERENCE DATA SYMBOL VDD IDD fOSC quiescent supply current clock oscillator frequency PARAMETER supply voltage range (pin 28) MIN. 4.5 - - MAX. 5.5 10 24 V A MHz UNIT
ORDERING AND PACKAGE INFORMATION EXTENDED TYPE NUMBER SAA1101P SAA1101T Notes 1. SOT117-1; 1996 December 02. 2. SOT136-1; 1996 December 02. 28 28 PACKAGE PINS DIL SO28 PIN POSITION MATERIAL plastic plastic CODE SOT117 (1) SOT136A (2)
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2
k, full pagewidth
January 1990
NORM 23 13 SI 3 24 160fH CS CB BK ID HD VD WMP CLP 12 RR LINE DIVIDER 17 16 15 22 21 20 19 40fH RESET PULSE SHAPER COMBINING LOGIC VERTICAL DIVIDER 2fH 18 ADDITION/ SUPPRESSION LOGIC
CS0 CS1 CLO
Philips Semiconductors
4
PRESCALER
OSCI
5
Universal sync generator (USG)
OSCO
6
X STANDARD PROGRAMMED DIVIDER VERTICAL LOCK VERTICAL DETECTION f SUBCARRIER SUBTRACTION Href HRI fs - f SUBCARRIER DIVIDER fH fH HORIZONTAL DETECTION
25 7 VLE
Y
26
Z
27
3
LOCK MODE SELECTION PHASE DETECTION 28 VSS 14 8 PH 9 10 LM1 LM0
11
ECS
FSI
1
fs
FSO
2
SAA1101
MGH191
VDD
SAA1101
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal sync generator (USG)
PINNING SYMBOL PIN
fpage
SAA1101
DESCRIPTION subcarrier oscillator input, where fmax = 5 MHz subcarrier oscillator output clock frequency selection - CMOS input clock frequency selection - CMOS input clock oscillator input, where fmax = 24 MHz clock oscillator output vertical in-lock enable - CMOS input phase detector output - 3-state output lock mode selection - CMOS input lock mode selection - CMOS input external composite sync. signal - CMOS Schmitt-trigger input frame reset - CMOS Schmitt-trigger input set identification, used to set the correct field sequence in PAL-mode. The correction (inversion of fH2) is done at the left-hand slope of the SI-pulse. Minimum pulse width is 800 ns. CMOS Schmitt-trigger input. ground identification - push-pull output burst key (PAL/NTSC), chroma-blanking (SECAM) push-pull output composite blanking - push-pull output composite sync. - push-pull output clamp pulse - push-pull output white measurement pulse-3-state output vertical drive pulse - push-pull output horizontal drive pulse - push-pull output used with X, Y and Z to select TV system; NORM = 0, 625/525 line mode (standard); NORM = 1, 624/524 line mode - CMOS input clock output - push-pull output TV system selection input - CMOS input TV system selection input - CMOS input TV system selection input - CMOS input voltage supply
FSI 1 FSO 2 CS1 3 CS0 4 OSCI 5 OSCO 6 VLE 7
28 VDD 27 Z 26 Y 25 X 24 CLO 23 NORM 22 HD
FSI FSO CS1 CS0 OSCI OSCO VLE PH LM1 LM0 ECS RR SI
1 2 3 4 5 6 7 8 9 10 11 12 13
SAA1101
PH 8 LM1 9 LM0 10 ECS 11 RR 12 SI 13 VSS 14
MGH190
21 VD 20 WMP 19 CLP 18 CS 17 CB 16 BK 15 ID
VSS ID BK CB
14 15 16 17 18 19 20 21 22 23
Fig.2
Pinning configuration; SOT117.
FUNCTIONAL DESCRIPTION Generation of pulses Generation of standard pulses such as sync, blanking and burst for TV systems: PAL B/G, PALN, PALM, SECAM and NTSC. In addition a number of non-standard pulses have been supplied to simplify signal processing. These signals include horizontal drive, vertical drive, clamp pulse, identification etc. It is possible to select the 524/624 line mode instead of the 525/625 line mode for all the above TV systems for applications such as robotics, games and computers.
CS CLP WMP VD HD NORM
CLO X Y Z VDD
24 25 26 27 28
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Philips Semiconductors
Product specification
Universal sync generator (USG)
Lock modes The USG offers four lock modes: * Lock from the subcarrier * Slow sync. lock, external Href * Slow sync. lock, internal Href * Fast sync. lock, internal Href LOCK FROM SUBCARRIER Lock from subcarrier to the line frequency for the above mentioned TV systems is given below; the horizontal frequency (fH) = 15.625 kHz for 625 line systems and 15.734264 kHz for 525 line systems. 0 0 1 1 SECAM (1 and 2) PALN NTSC (1 and 2) PALM PAL B/G 282fH 229.2516fH 227.5fH 227.25fH 283.7516fH LM0 0 1 0 1 LM1
SAA1101
subcarrier input is, in this case, used as an external input for the horizontal reference, see Fig.3(d). SELECTION OF LOCK MODE Lock mode is selected using the inputs LM0 and LM1 as illustrated in the Table below.
SELECTION lock to subcarrier slow sync. lock external Href slow sync. lock internal Href fast sync. lock internal Href
These relationships are obtained by the use of a phase locked loop and the internal programmed divider chain, see Fig.3(a). LOCK TO AN EXTERNAL SIGNAL SOURCE The following methods can be used to lock to an external signal source: 1. Sync. lock slow; the line frequency is locked to an external signal. The line and frame information are extracted from the external sync. signal and used separately in the lock system. The line information is used in a phase-locked loop where external and internal line frequencies are compared by the same phase detector as is used for the subcarrier lock. The external frame information is compared with the internal frame in a slow lock system; mismatch of internal and external frames will result in the addition or suppression of one line depending on the direction of the fault. The maximum lock time for frame lock is 6.25 s, see Fig.3(b). 2. Sync. lock fast. A fast lock of frames is possible with a frame reset which is extracted out of the incoming external sync. signal, see Fig.3(c). 3. Sync. lock with external reference. Lock of an external sync. signal to the line frequency with an external line reference to make possible a shifted lock. The
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Philips Semiconductors
Product specification
Universal sync generator (USG)
The different lock modes are illustrated by the following figures:
SAA1101
handbook, halfpage
n x fH LINE OSCILLATOR
handbook, halfpage
n x fH LINE OSCILLATOR
OSCO FSI 1 SUBCARRIER OSCILLATOR SAA1101 FSO 2 10 LM0 logic 0 9 6 5
OSCI 8 PH
OSCO ECS 11 SAA1101 6 5
OSCI 8 PH
10
9 LM1 logic 1
MGH195
LM1 logic 1
MGH193
LM0 logic 1
Fig.3 (a) Lock to subcarrier.
Fig.3 (c) Fast sync lock, internal H ref
handbook, halfpage
n x fH LINE OSCILLATOR
handbook, halfpage
n x fH LINE OSCILLATOR
OSCO ECS 11 SAA1101 6 5
OSCI 8 PH
FSI Href
HD 22 6 1
OSCO 5
OSCI 8 PH
SAA1101 ECS 11
10 LM0 logic 0
9 LM1 logic 1
MGH194
10 LM0 logic 0
9 LM1 logic 1
MGH192
Fig.3 (b) Slow sync lock, internal Href
Fig.3 (d) Slow sync lock, external H ref
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Philips Semiconductors
Product specification
Universal sync generator (USG)
LOCK WITH HORIZONTAL AND VERTICAL SIGNALS (slow lock modes only)
SAA1101
It is possible to use horizontal and vertical signals instead of composite sync signals. The connections in this situation are: the external horizontal signal is connected to the ECS input (pin 11) and the vertical signal to the RR input (pin 12). The HIGH time of the horizontal pulse must be less than 14.4 s, otherwise it will be detected as being a vertical pulse and will corrupt the vertical slow lock system. Selection of Clock Frequency The clock frequency is selected using the CS0 and CS1 inputs as illustrated below.
CS0 0 0 1 1 0 1 0 1
CS1
FREQUENCY 160fH 160fH 960fH 1440fH
625 LINES 2.5 5 15 22.5
525 LINES 2.517482 5.034964 15.104893 22.657340
UNITS MHz MHz MHz MHz
Where the horizontal frequency, fH = 15.625 kHz for 625 lines and 15.734264 kHz for 525 lines. Oscillators The subcarrier oscillator has FSI as its input and FSO as its output. It is always used as a crystal oscillator with a series resonance crystal with parallel load capacitor. The maximum frequency, fmax = 5 MHz and the load capacitor, CL = 10 < CL < 35 pF. The clock oscillator has OSCI as its input and OSCO as its output. It can be used with an LC oscillator or a series resonance crystal with parallel load capacitor (Fig.4). The maximum frequency, fmax = 24 MHz and the load capacitor, CL = 10 < CL < 35 pF. Selection of 625/525 (standard; interlaced mode) or 624/524 lines (non-interlaced mode) Selection is achieved using the NORM input. When NORM = 0, 625/525 (standard) lines are selected; when NORM = 1, 624/524 line are selected. Output Dimensions All push-pull outputs: standard output 2 mA. White measurement pulse, WMP: 3-state output 2 mA. Phase detector, PH: 3-state output 2 mA.
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Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
handbook, halfpage 39 pF
OSCI 5 500 k 6 OSCO
MGH196
15 MHz
SAA1101
39 pF
1 k
Fig.4 Crystal oscillator circuit.
Selection of TV System Selection of the required TV system is achieved by the X, Y and Z inputs as illustrated by the following Table.
SYSTEM SECAM1 PALN NTSC1 PALM SECAM2 PAL B/G NTSC2 0 0 0 0 1 1 1
X 0 0 1 1 0 0 1
Y 0 1 0 1
Z
0 (with identifier) 1 0 (short blanking)
LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDD VI II IO IDD Ptot Tstg Note 1. Input voltage should not exceed 7 V. input voltage maximum input current maximum output current maximum supply current in VDD maximum power dissipation storage temperature range PARAMETER supply voltage -0.5 -0.5 - - - - -55 MIN. +7 VDD + 0.5 10 10 25 400 +150
(1)
MAX. V V mA mA mA mW C
UNIT
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Philips Semiconductors
Product specification
Universal sync generator (USG)
CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = -25 to +70 C unless otherwise specified SYMBOL Supplies VDD IDD Inputs II VIH VIL VT+ VT- VH VIH VIL Outputs PUSH-PULL OUTPUTS; CB, CS, BK, ID, HD, VD, CLP AND CLO VOH VOL VOH VOL VOH VOL IOZ output voltage HIGH output voltage LOW output voltage HIGH output voltage LOW output voltage HIGH output voltage LOW OFF-state current -IO = 2 mA; VDD = 5 V IO = 2 mA; VDD = 5 V -IO = 0.75 mA; VDD = 5 V IO = 0.75 mA; VDD = 5 V -IO = 2 mA; VDD = 5V IO = 2 mA; V DD = 5V Tamb = 25 C 4.5 - 4.5 - 4.5 - - - - - - - - - input leakage current input voltage HIGH input voltage LOW positive-going threshold negative-going threshold hysteresis input voltage HIGH input voltage LOW Tamb = 25 C - - supply voltage supply current (quiescent) Tamb = 25 C 4.5 - - - PARAMETER CONDITIONS MIN. TYP.
SAA1101
MAX.
UNIT
5.5 10
V A
100 - 0.3VDD 4 - - - 0.3VDD
nA V V V V V V V
CMOS COMPATIBLE; X, Y, Z, NORM, CS0, CS1, LM0, LM1 AND VLE 0.7VDD - - - 1 0.4 - 2.5 1.5 1
SCHMITT TRIGGER INPUTS; ECS, RR AND SI
OSCILLATOR INPUTS; OSCI AND FSI 0.7VDD - - -
- 0.5 - 0.5 - 0.5 50
V V V V V V nA
OSCILLATOR OUTPUTS; OSCO AND FSO
3-STATE OUTPUTS; WMP AND PH
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full pagewidth
January 1990
start half picture tWCB 25H + tWCB 10H 9H(1)
1st half CS picture
Philips Semiconductors
OUTPUT WAVEFORMS
CS
2nd half picture
1st half CB picture
2nd half CB picture
VD
Universal sync generator (USG)
BK
1st half picture
BK
2nd half picture
CCIR/PAL
BK
3rd half picture
The output waveforms for the different modes of operation are illustrated by Figs 5 and 6.
10
BK
4th half picture
BK
1st half picture
SECAM-1
BK
2nd half picture
ID
1st half picture
ID
2nd half picture
MGH198
(1) H = 1 horizontal scan.
Product specification
SAA1101
Fig.5
Typical output waveforms for PAL/CCIR and SECAM. In the 624-line mode the output waveforms are identical to the first half picture of PAL/CCIR and are not interlaced.
ull pagewidth
January 1990
NTSC 1
(2)
Philips Semiconductors
Universal sync generator (USG)
start half picture CS 1st half picture 2nd half picture tWCB CB 1st half picture 21H + tWCB
CS
2nd half CB picture VD 1st half picture 2nd half picture 1st half picture 2nd half picture 3rd half picture 4th half picture 1st half picture 2nd half picture
MGH197
6H
BK NTSC 1 + 2
(2)
BK
9H 11H(1)
BK
11
BK PAL-M BK BK CB NTSC 2
(2)
19H + tWCB
CB
Product specification
(1) H = 1 horizontal scan. (2) NTSC mode reset; the fourth half picture is identical to the second half picture for NTSC.
SAA1101
Fig.6
Typical output waveforms for NTSC and PAL-M. In the 524-line mode the output waveforms are identical to the first half picture of NTSC and are not interlaced.
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
WAVEFORM TIMING The waveform timing depends on the frequency of the oscillator input (fOSCI). This is illustrated in the table below as the number (N) of oscillations at OSCI. The timings are derived from N x tOSCI 100 ns. One horizontal scan (H) = 320 x tOSCI =1/fH. Where tOSCI = 200 ns for PAL/SECAM and 198.6 ns for NTSC/PAL-M SYMBOL PARAMETER PAL NTSC PAL-M SECAM UNIT s s s H H N
Composite sync (CS) tWSC1 tWSC2 tWSC3 - - horizontal sync pulse width serration pulse width duration of pre-equalizing pulses duration of post-equalizing pulses duration of serration pulses 4.8 4.77 2.38 4.77 3 3 4.77 2.38 4.77 3 3 4.8 2.4 4.8 2.5 2.5 24 12 24 - -
equalizing pulse width 2.4 4.8 2.5 2.5
-
2.5
3
3.5
2.5
H
-
Composite blanking (CB) HORIZONTAL BLANKING PULSE WIDTH tWCB tWCB tWCB tPCBCS - - - PAL/SECAM/PAL-M NTSC1 NTSC2 12 - - - 11.12 10.53 (note1) 11.12 - - 12 - - s s s s - - - s s H - - - - 60 56 53
FRONT PORCH front porch 1.6 25H + tWCB - - 1.59 - 21H + tWCB 19H + tWCB 2.38 5.56 9 1.59 21H + tWCB - - 1.6 25H + tWCB - - - - - - - - - 8 - - -
DURATION OF VERTICAL BLANKING PAL/SECAM/PAL-M NTSC1 NTSC2
Burst key (BK) (not SECAM) tWBK tPCSBK - - - - - burst key pulse width burst suppression 2.4 9 2.38 5.76 11 12 28 - - - - - CS to burst key delay 5.6
POSITION OF BURST SUPPRESSION first half picture second half picture third half picture fourth half picture H623 to H6 H310 to H318 H622 to H5 H311 to H319 H523 to H6 H261 to H269 H523 to H6 H261 to H269 H523 to H8 H260 to H270 H522 to H7 H259 to H269
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Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
SYMBOL
PARAMETER - - - -
PAL - - - -
NTSC - - - -
PAL-M
SECAM
UNIT s s - - s s s s s
N
Burst key (BK) (SECAM) tWBK tPBKCS - - chroma pulse width CS to chroma delay 7.2 1.6 36 8 - -
DURATION OF VERTICAL BLANKING SECAM1 SECAM2 note 2 note 3
Clamp pulse (CLP) tWCLP tPCSCLP tWHD tPHDCS - - tPVDCS - - - - - clamp pulse width CS to CLP delay 2.4 1.6 2.38 1.59 2.38 1.59 2.4 1.6 12 8
Horizontal drive (HD) pulse width CS to HD delay repetition period 7.2 0.8 64 7.15 0.79 63.56 7.15 0.79 63.56 7.2 0.8 64 36 4 - - 8
Vertical drive (VD) VD duration CS to VD delay 10 1.6 6 1.59 6 1.59 10 1.6 H s s s H - - s s - -
White measurement pulse (WMP) pulse width CS to WMP delay duration of WMP 2.4 34.4 10 2.38 34.16 9 2.38 34.16 9 2.4 34.4 10 12 172 - - -
POSITION OF WMP first half picture second half picture H163 to H173 H475 to H485 H134 to H143 H396 to H405 H134 to H143 H396 to H405 H163 to H173 H475 to H485
Identification (ID) tWID tPIDCS - - pulse width CS to ID delay first half picture second half picture 12 1.6 H7 to H15 H320 to H328 11.12 1.59 H8 to H22 H271 to H285 11.12 1.59 H8 to H22 H271 to H285 12 1.6 H7 to H15 H320 to H328 60 8 - -
POSITION OF ID
Notes to the characteristics 1. Horizontal blanking pulse width for NTSC2 can be 11.12 s maximum 2. SECAM1, first half picture: 25H + tWBK except H320 to H328. Second half picture: 24.5H + tWBK except H7 to H15. 3. SECAM2, first half picture: 25H + tWBK. Second half picture: 24.5H + tWBK.
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Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
handbook, full pagewidth
horizontal sync pulse CS equalizing pulse t WSC3
t WSC1 t WSC2
composite sync
serration pulse composite blanking horizontal blanking pulse
CB
t WCB t PCBS2 t PCBSK t WBK
burst key (PAL) burst key/ chrominance BK blanking (SECAM) chrominance blanking horizontal drive t PHDCS CLP clamp pulse t PCSCLP ID SECAM identification t PIDCS VD start, stop vertical drives
t WBK t PBKCS t WHD t WCPL t WID
HD
t PVDCS
MLA029
Fig.7 Waveform timing.
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Philips Semiconductors
Product specification
Universal sync generator (USG)
PACKAGE OUTLINES
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth
SAA1101
SOT117-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 28 15 MH wM (e 1)
pin 1 index E
1
14
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
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Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.050 0.055 0.394 0.016
0.035 0.004 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Product specification
Universal sync generator (USG)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
SAA1101
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Universal sync generator (USG)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA1101
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1990
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